Analog · ASIC · Mixed-Signal · Medical

Where Silicon
Meets Precision

The world's foremost analog IC design house. We push the absolute boundaries of what analog silicon can achieve — from 56 GSps data converters to life-critical medical ASICs.

Explore Capabilities Engage Our Team
56 GSps ADC
48 GSps DAC
32G SerDes bps
ADC DESIGN  ·  DAC DESIGN  ·  PLL  ·  SERDES  ·  MEDICAL ASIC  ·  SENSOR INTERFACE  ·  MIXED-SIGNAL  ·  BOARD DESIGN  ·  HIGH-SPEED ANALOG  ·  FDA-GRADE DESIGNS  ·  CMOS LAYOUT  ·  CHIP TAPE-OUT  ·  ADC DESIGN  ·  DAC DESIGN  ·  PLL  ·  SERDES  ·  MEDICAL ASIC  ·  SENSOR INTERFACE  ·  MIXED-SIGNAL  ·  BOARD DESIGN  ·  HIGH-SPEED ANALOG  ·  FDA-GRADE DESIGNS  ·  CMOS LAYOUT  ·  CHIP TAPE-OUT  · 

Begin Your
Next Breakthrough

Whether you have a defined spec or an ambitious idea, our team can turn it into silicon reality. We engage on NDA before any technical discussion.

Company GigaLog Ltd.
Web gigalogchip.com
Specialty Analog IC, ASIC Design, Medical Electronics, High-Speed Data Converters
Scope Global — NDA-first engagement, foundry-agnostic

This will open your email client with all fields pre-filled,
addressed to miki@gigalogchip.com

02 — Knowledge Transfer

Teaching at the
Frontier of Analog

Dr. Moyal lectures on advanced data converter architectures at leading universities — the same IP that powers production silicon.

Dr. Miki Moyal teaching 56 Gbps ADC design at a university lecture
University Lecture
Teaching the World's
56 Gbps ADC
Dr. Moyal lectures on advanced data converter architectures at leading universities — sharing the same IP that powers production silicon in 400G optical networks.
03 — What We Do

Engineering at the
Edge of Physics

From concept to silicon, we master every layer of analog and mixed-signal IC design — delivering IPs that are benchmarks in their class.

001
ASIC Design
Full-custom and semi-custom ASIC development from specification through tape-out. We own the complete flow — schematic, layout, verification, and silicon bring-up.
Full-Custom GDS-II LVS/DRC Post-Silicon
002
High-Speed ADC & DAC
World-record performance data converters. Our ADCs reach 56 GSps with 6-bit ENOB; DACs push 48 GSps. Designed for optical comms, radar, and test instrumentation.
56 GSps ADC 48 GSps DAC SAR / Flash Sigma-Delta
003
PLL & SerDes Cores
Ultra-low-jitter PLLs and multi-gigabit SerDes IPs for high-speed communications. Our 32 Gbps SerDes core is deployed in production optical transceivers worldwide.
32 Gbps Sub-ps Jitter CDR PAM4
004
Medical ASICs
Proven portfolio of life-critical ICs — biopotential amplifiers, implantable sensor ASICs, neural recording front-ends. Designed to IEC 60601 and ISO 13485 standards.
IEC 60601 ISO 13485 Ultra-Low Power Implantable
005
Sensor Interfaces
Precision analog front-ends for resistive, capacitive, inductive, and optical sensors. Optimized for industrial IoT, wearable medical, and environmental monitoring.
Capacitive Resistive Optical MEMS
006
Board & System Design
High-speed PCB design for analog-intensive systems. Signal integrity, power integrity, and EMC managed at every layer. From prototype to production-ready Gerbers.
High-Speed PCB SI / PI EMC Thermal
56 GSps Max ADC Rate
48 GSps Max DAC Rate
32G bps SerDes Core
<100 fs RMS Jitter (PLL)
7nm Minimum Node
100+ Successful Tape-Outs
ADC PGA DSP PLL
Proven Medical ASIC
ISO 13485 Certified

Life-Critical
Silicon

Our medical ASIC portfolio spans implantable devices, diagnostic instruments, and wearable biosensors — where failure is not an option.

05 — Technical Excellence

Performance That
Defies Convention

Every number below represents a world-class achievement — results from silicon proven in production, not simulations.

56G
Samples/sec ADC — world-leading flash architecture with 6-bit ENOB for optical coherent receivers
48G
Samples/sec DAC — 8-bit resolution, deployed in 400G optical transponders and advanced test equipment
32G
bps SerDes — proprietary CDR architecture with equalization, <1 ps RMS jitter on the recovered clock
<1µV
Input-referred noise on medical biopotential front-ends — enabling detection of sub-threshold neural activity
120dB
Dynamic range in precision optical TIA arrays — enabling single-photon-level measurements in diagnostics
7nm
Minimum CMOS process node deployed — with full custom analog layout expertise in nodes from 180 nm to 7 nm
10µW
Per-channel power in neural recording ASIC — sustaining multi-year battery life for chronic implants
100fs
RMS jitter from on-chip PLL — enabling multi-channel ADC synchronization for phased-array applications

Analog Mastery
Across Every Domain

Decades of cumulative expertise concentrated in a single design team. We hire only those who can claim world-class standing in their specialty.

High-Speed Data Converters 98%
Medical & Bio-Analog ICs 96%
PLL / Clock Architecture 95%
SerDes & High-Speed I/O 94%
Sensor Interface & AFE 97%
RF & Wireless IC Design 88%
20+
Years in Analog IC Design
Deep institutional knowledge in analog silicon, from bipolar-era circuits to sub-10nm CMOS.
100+
Successful Silicon Tape-Outs
Over a hundred designs taken to tape-out — each meeting or exceeding its performance specification on first silicon.
8
Active Foundry Partnerships
TSMC, GlobalFoundries, TowerSemi, UMC, XFAB, and more — giving you process flexibility.
3
Continents Served
Global client base in medical devices, optical networking, defense, and industrial sensing.
5
University Lecture Programs
Our senior designers teach advanced analog IC courses at top universities — shaping the field's next generation.
∞
Performance Ambition
We don't accept "good enough." Every design targets a new benchmark in its class.
07 — Portfolio

Silicon Delivered.
Proven in Production.

A selection of real tape-outs, PCBs, die photographs, and deployed medical systems — every image from an actual GigaLog project.

IC Layout GDS
IC Layout
High-Speed ADC GDS Layout
Full custom analog layout — time-interleaved flash ADC, sub-micron CMOS. Green: diffusion, Red: metal, Blue: poly.
Full Chip Die
Die Photo
Full Chip Die — Mixed-Signal ASIC
Actual die photograph of a taped-out GigaLog mixed-signal ASIC. Macro blocks: ADC array, PLL, digital core, I/O ring.
GigaLog Die
Die Photo
GigaLog Branded Die
Production die with GigaLog marking — analog ASIC in advanced CMOS node.
Wire Bond
Die Inspection
Wire Bond Microscopy
Gold wire bonds under optical microscope — post-package inspection of analog I/O pads.
IC Layout
IC Layout
Mixed-Signal GDS View
Detailed view of analog layout — matched transistor arrays, shielded routing, precision current mirrors.
Die Photo
Die Photo
ASIC Die — Bond Wire Detail
Close-up of die bond pad ring and gold ball bonds on a taped-out GigaLog ASIC.
Chip Floorplan
Chip Floorplan
Full-Chip Floorplan — SoC
Complete chip floorplan for a mixed-signal SoC. Blocks include: ADC array, DAC, PLL, SerDes lanes, digital backend, I/O ring, ESD structures.
CT Detector
Medical System
CT Detector — Medical Imaging System
GigaLog-designed detector array and readout ASICs for CT medical imaging. Includes curved PCB assembly, eye diagram, and sensor module CAD.
Dental ASIC
Medical ASIC
CMOS Dental X-Ray Sensor ASIC
Custom CMOS image sensor ASIC for intraoral dental X-ray — PN: A1000271. GigaLog-designed readout IC on medical-grade substrate.
SunDAQ CZT
Nuclear Medicine
SunDAQ CZT-256 Imaging Board
256-channel CZT nuclear detector readout board. GigaLog ASIC interface for gamma-ray imaging and nuclear medicine diagnostics.
Implant Module
Medical · Implantable
Wireless Implant Module
Ultra-miniature round PCB for implantable device — low-power analog front-end, wireless power and data link in a <20mm form factor.
High-Speed PCB
Board Design
High-Speed Mixed-Signal PCB
Xilinx Spartan-6 FPGA + Linear Technology LTM4619V µModule power supply. GigaLog-designed high-density multi-layer board for ADC evaluation platform.
PCB Board
Board Design
ADC Evaluation Board
Dense mixed-signal PCB with Spartan-6, muRata isolated DC/DC, precision resistor networks. Ground plane isolation and controlled-impedance routing throughout.
Lab Setup
Silicon Bring-Up
Board Bring-Up — Lab
Post-assembly bring-up of a GigaLog analog board — component illumination test and power rail verification.
PCB Detail
PCB Inspection
GigaLog Board — Microscope View
Optical inspection of GigaLog branded PCB assembly — solder joint quality control and component placement verification.
ASIC Package
IC Package
Ceramic ASIC Package
Gold-leaded ceramic QFP package housing a GigaLog custom ASIC — hermetically sealed for aerospace and medical reliability requirements.
Die on Probe
Wafer Test
Die Under Probe Station
Wafer-level probing during post-silicon characterisation — analog performance verified at die level before packaging.
08 — Foundry Partners

Silicon Made at the
World's Best Fabs

We maintain active design kits and proven methodologies at eight of the world's leading semiconductor foundries.

09 — Founder

Built by One of the
World's Foremost Analog Minds

Dr. Miki Moyal — Founder, GigaLog
Dr. Miki Moyal
Founder & Chief Analog Architect
IEEE Author US Patents ADC Pioneer
Career Milestones
AMD High-speed flash & interleaved ADC IPs
TI Founded analog IP company, acquired by Texas Instruments
MRVL SerDes & equalizer architecture, Marvell M.I.S.L.
GL Founded GigaLog — world-class analog design house

"There are engineers who design to specification — and there are those who redefine what specifications are possible. Miki Moyal is the latter."

Dr. Miki Moyal (also known as Michael Moyal) is a world-renowned analog IC architect whose career spans more than two decades at the absolute frontier of silicon performance. Holding a doctorate in electrical engineering and an extensive portfolio of US patents, he is one of a small number of engineers globally who can claim to have personally designed multiple world-record ICs in production silicon.

His early career at Advanced Micro Devices (AMD) produced foundational patents in high-speed flash ADC architectures and time-interleaved analog-to-digital conversion — techniques that remain central to data converter design today. His parallel-interleaved ADC architecture patent at AMD addressed the fundamental speed ceiling of monolithic flash converters, enabling sampling rates previously considered unachievable in CMOS.

Dr. Moyal subsequently founded an analog IC company specialising in precision PLL and mixed-signal design, which was acquired by Texas Instruments. His TI-assigned patent in compact PLL design — reducing loop filter area while preserving phase noise performance — reflects a characteristic approach: achieving more with less silicon. He went on to contribute to Marvell M.I.S.L., where he co-invented novel SerDes equalizer architectures for multi-gigabit communications.

He is widely recognized as a pioneer of continuous-time sigma-delta ADC architectures — a class of converters that obviate the discrete-time sampling bottleneck, enabling far wider signal bandwidths and inherent anti-aliasing. His work in this area spans current-mode CT-ΣΔ loops, noise-shaping techniques, and jitter-tolerant feedback DAC structures, forming the basis of multiple granted US patents and IEEE publications.

Dr. Moyal founded GigaLog Ltd. to bring these capabilities to clients worldwide — with a deliberate focus on the highest-performance, highest-stakes applications: 56 GSps data converters for optical communications, 32 Gbps SerDes for wireline infrastructure, and life-critical ASICs for the medical devices market. His lectures at leading universities continue to shape the next generation of analog IC designers.

Selected Patent Portfolio
Time-Interleaved Flash ADC
Assignee: Advanced Micro Devices
Compact PLL with Reduced Loop Filter
Assignee: Texas Instruments Inc. (US 7154345)
CT-ΣΔ ADC with Current-Mode Mixer
Continuous-time sigma-delta architecture
SerDes Equalizer Architecture
Assignee: Marvell M.I.S.L. (US 9143368)